CLHR=STANDARD, BITO=OFF, CLTO=OFF
Control Register
EN | I2C Enable |
SLAVE | Addressable as Slave |
AUTOACK | Automatic Acknowledge |
AUTOSE | Automatic STOP When Empty |
AUTOSN | Automatic STOP on NACK |
ARBDIS | Arbitration Disable |
GCAMEN | General Call Address Match Enable |
TXBIL | TX Buffer Interrupt Level |
CLHR | Clock Low High Ratio 0 (STANDARD): The ratio between low period and high period counters (Nlow:Nhigh) is 4:4 1 (ASYMMETRIC): The ratio between low period and high period counters (Nlow:Nhigh) is 6:3 2 (FAST): The ratio between low period and high period counters (Nlow:Nhigh) is 11:6 |
BITO | Bus Idle Timeout 0 (OFF): Timeout disabled 1 (40PCC): Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 2 (80PCC): Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 3 (160PCC): Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. |
GIBITO | Go Idle on Bus Idle Timeout |
CLTO | Clock Low Timeout 0 (OFF): Timeout disabled 1 (40PCC): Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 2 (80PCC): Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 3 (160PCC): Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 4 (320PCC): Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 5 (1024PCC): Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. |